The present disclosure relates to integrated circuit (IC) testing, and, more particularly, to logic built-in self-test (LBIST) circuitry and the like.
Built-in self-test (BIST) is a mechanism that enables a machine or system to test itself. Engineers use BIST to meet customer specifications and/or to reduce reliance upon external test equipment in making the determination of whether or not a device or circuit under test (DUT or CUT) works properly. In some cases, a BIST mechanism may be used to test device circuitry that is not otherwise accessible for testing from the device exterior. In the context of an integrated circuit, logic BIST (LBIST) is a form of BIST in which the corresponding hardware and/or software is built into the IC to enable the IC to test its own operation. A similar testing approach alternatively can be implemented using automatic test pattern generation (ATPG) instead of or in addition to LBIST.
One of the challenges in generating at-speed scan tests is to avoid false failures due to exercising paths that are not designed to propagate logic values within a single clock cycle or paths that are functionally asynchronous. These paths are known as timing-exception paths, examples of which include false paths and multi-cycle paths. False paths are not exercisable in the functional mode of operation, but may be exercisable during scan testing. Multi-cycle paths are designed such that the expected values are only available at the destination node after some specified number of clock cycles. These paths, if exercised during at-speed capture, may lead to the capture of an unknown value (often referred to in the relevant literature as an “X”), thereby corrupting the test signature(s). Current methodology in the industry tends to mask these paths from at-speed testing (e.g., using SDC: Synopsys Design Constraints). Masking these paths through SDC can be done, e.g., by X-propagation of data from the launch registers (of timing exception related paths). This however may lead to test-coverage loss, as valid paths get masked due to the X-propagation.
Techniques implemented in ICs for the purpose of controlling various types of X-propagation during LBIST/ATPG testing are generally referred to as “X-bounding”. The present invention generally relates to X-bounding of timing-exception paths in at-speed scan testing.
For example, in some conventional ICs, X-bounding may be implemented by inserting one or more dedicated logic gates, flip-flops, latches, registers, multiplexers, and/or other suitable circuit elements into a respective safe-stating point corresponding to each relevant X-propagation path. However, this approach may disadvantageously lengthen critical paths, increase the die area, and/or increase the IC's power consumption. In addition, the predetermined logic outputs of the inserted safe-stating circuit elements may propagate through downstream logic, thereby limiting the effective test patterns that can be applied for testing the IC and/or reducing the percentage of the logic circuitry that can be covered by the tests.